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document number: mc34717 rev 4.0, 12/2008 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007-8. all rights reserved. 5.0 a 1.0 mhz fully integrated dual switch-mode power supply the 34717 is a highly integrated, s pace-efficient, low cost, dual synchronous buck switching regulator with integrated n-channel power mosfets. it is a high perf ormance dual point-of-load (pol) power supply with many desired features for the 3.3 and 5.0 v environments. both channels can provide up to 5.0 a of continuous output current capability with high efficiency and tight output regulation. the second channel has the ability to track an external reference voltage in different configurations. the 34717 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. it is housed in a pb-free, thermally enhanced, and space efficient 26 pin exposed pad qfn. features ?50 m integrated n-channel power mosfets ? input voltage operating range from 3.0 to 6.0 v ? 1% accurate output voltages, ranging from 0.7 to 3.6 v ? the second output has voltage tracking capability in different configurations ? programmable switching frequency range from 200 khz to 1.0 mhz ? programmable soft start timing ? over-current limit and short-circuit protection ? thermal shutdown ? output over-voltage and under-voltage detection ? active low power good output signal ? active low shutdown input ? pb-free packaging designated by suffix code ep. figure 1. 34717 simplified application diagram dual switch-mode power supply ep suffix (pb_free) 98asa10728d 26-pin qfn 34717 ordering information device temperature range (t a ) package mc34717ep/r2 -40 to 85c 26 qfn vin pvin1 3.0 to 6.0 v boot1 sw1 inv1 comp1 vout1 gnd vrefin vddi freq pg 34717 v in v out1 pgnd1 pvin2 boot2 sw2 inv2 comp2 vout2 pgnd2 ilim1 v master ilim2 sd mcu v out2 v out1 v in optional
analog integrated circuit device data 2 freescale semiconductor 34717 internal block diagram internal block diagram figure 2. 34717 simplifi ed internal block diagram sd vin boot2 pvin1 sw1 pgnd1 comp2 inv1 vout1 vddi ilim1 freq gnd vrefin boot1 pvin2 sw2 pgnd2 comp1 inv2 vout2 system reset oscillator buck control logic current monitoring system control thermal monitoring bandgap regulator internal voltage regulator gate driver gate driver ramp generator ramp generator discharge v bg m1 i sense1 i sense2 i lim1 i lim2 m6 m7 i sense m4 m5 i sense f sw f sw v in v in m3 + ? + ? error amplifier pwm comparator + ? + ? error amplifier pwm comparator v bg m8 discharge m9 discharge f sw reference selection v bg m2 ilim2 pg channel 2 channel 1
analog integrated circuit device data freescale semiconductor 3 34717 pin connections pin connections figure 3. 34717 pin connections table 1. 34717 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name pin function formal name definition 1 boot1 passive bootstrap channel 1 bootstrap capacitor input pin 2 pvin1 supply power input voltage channel 1 buck converter power input 3 sw1 output switching node channel 1 buck converter switching node 4 pgnd1 ground power ground channel 1 buck converter and discharge mosfets power ground 5 vout1 output output voltage discharge path channel 1 buck converter out put voltage discharge pin 6 inv1 input error amplifier inverting input channel 1 buck converter erro r amplifier inverting input 7 comp1 input buck convertor compensation input channel 1 buck converter exter nal compensation network input 8 vrefin input reference voltage input voltage tracking reference voltage input 9, 26 nc none no connect no internal connections to this pin. recommend attaching a 0.1 f capacitor from pin 9 to gnd. 10 pg output power good output signal it is an active low open drain power good status reporting output 11 sd input shutdown input shutdown mode input control pin 12 comp2 input buck convertor compensation input channel 2 buck converter exter nal compensation network input 13 inv2 input error amplifier inverting input channel 2 buck converter erro r amplifier inverting input transparent top view 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 boot1 pvin1 sw1 pgnd1 vout1 inv1 comp1 vrefin nc pg sd comp2 inv2 vout2 pgnd2 sw2 pvin2 boot2 ilim1 ilim2 freq vin vin gnd vddi nc pvin2 sw2 pgnd2 pgnd1 sw1 pvin1 pin 27
analog integrated circuit device data 4 freescale semiconductor 34717 pin connections 14 vout2 output output voltage discharge path channel 2 buck converter out put voltage discharge pin 15 pgnd2 ground power ground channel 2 buck converter and discharge mosfets power ground 16 sw2 output switching node channel 2 buck converter switching node 17 pvin2 power power input voltage channel 2 buck converter power input 18 boot2 input bootstrap input channel 2 bootstrap capacitor input pin 19 ilim1 input soft start adjustment input ch 1 channel 1 soft start adjustment 20 ilim2 input soft start adjustment input ch 2 channel 2 soft start adjustment 21 freq input frequency adjustment input the buck converters switching frequency adjustment input 22,23 vin power input supply voltage power supply voltage of the ic 24 gnd ground signal ground analog ground of the ic 25 vddi output internal supply voltage internal supply voltage output 27 gnd ground thermal pad thermal pad for heat transfer. connect the thermal pad to the analog ground and the ground plane for heat sinking. table 1. 34717 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 12 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 34717 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings input supply voltage (vin) pin v in -0.3 to 7.0 v high side mosfet drain voltage (pvin1, pvin2) pins pv in -0.3 to 7.0 v switching node (sw1, sw2) pins v sw -0.3 to 7.0 v boot1, boot2 pins (referenced to sw1, sw2 pins respectively) v boot - v sw -0.3 to 7.0 v pg , vout1, vout2, and sd pins - -0.3 to 7.0 v vddi, freq, ilim1, ilim2, inv1, inv2, comp1, comp2, and vrefin pins - -0.3 to 3.0 v channel 1 continuous output current (1) i out1 +5.0 a channel 2 continuous output current (1) i out2 +5.0 a esd voltage (2) human body model machine model (mm) charge device model v esd1 v esd2 v esd3 2000 200 750 v thermal ratings operating ambient temperature (3) t a -40 to 85 c storage temperature t stg -65 to +150 c peak package reflow temperature during reflow (4) , (5) t pprt note 5 c maximum junction temperature t j(max) +150 c power dissipation (t a = 85c) (6) p d 2.03 w notes 1. continuous output current capability so long as t j is t j(max) . 2. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ), the machine model (mm) (c zap = 200 pf, r zap = 0 ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 3. the limiting factor is junction temperature, taking into account power dissipation, ther mal resistance, and heatsinking. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 6. maximum power dissipation at indicated ambient temperature.
analog integrated circuit device data 6 freescale semiconductor 34717 electrical characteristics maximum ratings thermal resistance (7) thermal resistance, junction to ambient, single-layer board (1s) (8) r ja 93 c/w thermal resistance, junction to ambient, four-layer board (2s2p) (9) r q jma 32 c/w thermal resistance, junction to board (10) r q jb 13.6 c/w notes 7. the pvin, sw, and pgnd pins comprise the main heat conduction paths. 8. per semi g38-87 and jedec jesd51-2 with th e single-layer board (jesd51-3) horizontal. 9. per jedec jesd51-6 with the board (jesd51-7) horizontal. there are thermal vias connecting the package to the two planes in t he board. (per jesd51-5) 10. thermal resistance between the device and the printed circuit board per jedec jesd51- 8. board temperature is measured on the top surface of the board near the package. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data freescale semiconductor 7 34717 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit ic input supply voltage (vin) input supply voltage operating range v in 3.0 - 6.0 v input dc supply current (11) (normal mode: sd = 1, unloaded outputs) i in - - 35 ma input dc supply current (11) (shutdown mode, sd = 0) i inoff - - 100 a internal supply voltage output (vddi) internal supply voltage range v ddi 2.35 2.5 2.65 v channel 1 buck converter (pvin1, sw1, pgnd1, boot1, inv1, comp1, ilim1) channel 1 high side mosfet drain voltage range p vin 2.5 - 6.0 v output voltage adjustment range (12) v outhi1 0.7 - 3.6 v output voltage accuracy (12) , (13) - -1.0 - 1.0 % line regulation (12) (normal operation, v in = 3.0 to 6.0 v, i out1 = 2.5 a) reg ln1 -1.0 - 1.0 % load regulation (12) (normal operation, i out1 = 0.0 to 5.0 a) reg ld1 -1.0 - 1.0 % error amplifier reference voltage (12) v ref1 - 0.7 - v output under-voltage threshold v uvr1 -8.0 - -1.5 % output over-voltage threshold v ovr1 1.5 - 8.0 % continuous output current i out1 - - 5.0 a over-current limit i lim1 - 6.5 - a soft start adjusting reference voltage range v ilim1 1.25 - v ddi v short-circuit current limit i short1 - 8.5 - a high side n-ch power mosfet (m4) r ds(on) (12) (i out1 = 1.0 a, v boot1 - v sw1 = 3.3 v) r ds(on)hs1 10 - 50 m low side n-ch power mosfet (m5) r ds(on) (12) (i out1 = 1.0 a, v in = 3.3 v) r ds(on)ls1 10 - 50 m m2 r ds(on) (v in = 3.3 v, m2 is on) r ds(on)m2 2.0 - 4.0 notes 11. section ?modes of operation?, page 16 has a detailed description of the different operating modes of the 34717 12. design information only, this parameter is not production tested. 13. this is directly affected by the accuracy of the exte rnal feedback network, 1% feedback resistors are recommended.
analog integrated circuit device data 8 freescale semiconductor 34717 electrical characteristics static electrical characteristics sw1 leakage current (standby and shutdown modes) i sw -10 - 10 a pvin1 pin leakage current (shutdown mode) i pvin1 -10 - 10 a error amplifier dc gain (14) a ea - 150 - db error amplifier unit gain bandwidth (14) ugbw ea - 3.0 - mhz error amplifier slew rate (14) sr ea - 7.0 - v/s error amplifier input offset (14) offset ea -3.0 0 3.0 mv inv1 pin leakage current i inv1 -1.0 - 1.0 a thermal shutdown threshold (14) t sdfet1 - 170 - c thermal shutdown hysteresis (14) t sdhyfet1 - 25 - c channel 2 buck converter (pvin2, sw2, pgnd2, boot2, inv2, comp2, ilim2) channel 2 high side mosfet drain voltage range p vin 2.5 - 6.0 v output voltage adjustment range (14) v outhi2 0.7 - 3.6 v output voltage accuracy (14) , (15),(16) - -1.0 - 1.0 % line regulation (14) (normal operation, v in = 3.0 to 6.0 v, i out2 = 2.5 a) reg ln2 -1.0 - 1.0 % load regulation (14) (normal operation, i out2 = 0.0 to 5.0 a) reg ld2 -1.0 - 1.0 % error amplifier reference voltage (14) v ref2 - 0.7 - v output under-voltage threshold v uvr2 -8.0 - -1.5 % output over-voltage threshold v ovr2 1.5 - 8.0 % continuous output current i out2 - - 5.0 a over-current limit i lim2 - 6.5 - a soft start adjusting reference voltage range v ilim2 1.25 - v ddi v short-circuit current limit i short2 - 8.5 - a high side n-ch power mosfet (m6) r ds(on) (14) (i out2 = 1.0 a, v boot2 - v sw2 = 3.3 v) r ds(on)hs2 10 - 50 m low side n-ch power mosfet (m7) r ds(on) (14) (i out2 = 1.0 a, v in = 3.3 v) r ds(on)ls2 10 - 50 m m3 r ds(on) (v in = 3.3 v, m3 is on) r ds(on)m3 2.0 - 4.0 sw2 leakage current (standby and shutdown modes) i sw -10 - 10 a pvin2 pin leakage current (shutdown mode) i pvin2 -10 - 10 a notes 14. design information only, this parameter is not production tested. 15. this is directly affected by the accuracy of the exte rnal feedback network, 1% feedback resistors are recommended. 16. 1% is assured at room temperature table 3. static elec trical characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 34717 electrical characteristics static electrical characteristics error amplifier dc gain (17) a ea - 150 - db error amplifier unit gain bandwidth (17) ugbw ea - 3.0 - mhz error amplifier slew rate (17) sr ea - 7.0 - v/s error amplifier input offset (17) offset ea -3.0 0 3.0 mv inv2 pin leakage current i inv2 -1.0 - 1.0 a thermal shutdown threshold (17) t sdfet2 - 170 - c thermal shutdown hysteresis (17) t sdhyfet2 - 25 - c oscillator (freq) oscillator frequency adjusting reference voltage range v freq 0.0 - v ddi v tracking (vrefin, vout1, vout2) vrefin external reference voltage range (17) v refin 0.0 - 1.35 v vout1 total discharge resistance (17) r tds(m8) - 50 - vout2 total discharge resistance (17) r tds(m9) - 50 - control and supervisory ( sd , pg ) sd high level input voltage v sdhi 2.0 - - v sd low level input voltage v sdlo - - 0.4 v sd pin internal pull-up resistor r sdup 1.0 - 2.0 m pg low level output voltage (i pg = 3.0 ma) v pglo - - 0.4 v pg pin leakage current (m1 is off, pulled up to vin) i pglkg -1.0 - 1.0 a notes 17. design information only, this parameter is not production tested. table 3. static elec trical characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 34717 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit channel 1 buck converter (pvin1, sw1, pgnd1, boot1, inv1, comp1, ilim1) switching node (sw1) rise time (18) (p vin = 3.3 v, i out1 = 5.0 a) t rise1 - 8.0 - ns switching node (sw1) fall time (18) (p vin = 3.3 v, i out1 = 5.0 a) t fall1 - 5.0 - ns minimum off time t offmin - 150 - ns minimum on time t onmin - 0 (19) - ns soft start duration (normal mode) ilim1: 1.25 to 1.49 v 1.5 to 1.81 v 1.82 to 2.13 v 2.14 to 2.5 v t ss1 - - - - 3.2 1.6 0.8 0.4 - - - - ms over-current limit timer t lim1 - 10 - ms over-current limit retry timeout period t timeout1 80 - 120 ms output under-voltage/over-voltage filter delay timer t filter1 5.0 - 25 s channel 2 buck converter (pvin2, sw2, pgnd2, boot2, inv2, comp2, ilim2) switching node (sw2) rise time (18) (p vin = 3.3 v, i out2 = 5.0 a) t rise2 - 28 - ns switching node (sw2) fall time (18) (p vin = 3.3 v, i out2 = 5.0 a) t fall2 - 12.0 - ns minimum off time t offmin - 150 - ns minimum on time t onmin - 0 (19) - ns soft start duration (normal mode) ilim2: 1.25 to 1.49 v 1.5 to 1.81 v 1.82 to 2.13 v 2.14 to 2.5 v t ss2 - - - - 3.2 1.6 0.8 0.4 - - - - ms over-current limit timer t lim2 - 10 - ms over-current limit retry timeout period t timeout2 80 - 120 ms output under-voltage/over-voltage filter delay timer t filter2 5.0 - 25 s oscillator (freq) (20) notes 18. design information only, this parameter is not production tested. 19. the regulator has the ability to enter into pulse skip mode when the inductor current ripple reaches the threshold for the l s zero detect, which has a typical value of 500 ma. 20. oscillator frequency is 10%
analog integrated circuit device data freescale semiconductor 11 34717 electrical characteristics dynamic electrical characteristics oscillator default switching frequency (freq = gnd) f sw - 1.0 - mhz oscillator switching frequency range f sw 200 - 1000 khz control and supervisory ( sd , pg ) pg reset delay t pgreset 8.0 - 12 ms thermal shutdown retry timeout period (21) t timeout 80 - 120 ms notes 21. design information only, this parameter is not production tested. table 4. dynamic elec trical characteristics characteristics noted under conditions 3.0 v v in 6.0 v, - 40 c t a 85 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 34717 functional description introduction functional description introduction today?s advanced systems ar e increasingly requiring more efficient and accurate power supplies. they present a set of challenges that include highly accurate voltage regulation, high current and fast transient response capability, voltage monitoring (power sequencing), and increased operating frequency. point of load power supplies offer adequate solutions to these challenges. they are non- isolated dc to dc converters that are located near their load and take their input voltage from an intermediate not, necessarily, regulated bus. their close proximity to the load is of a high importance with newer device requirements. while meeting the challenges, they allow for higher efficiency, localized protection, and minimum distribution losses. their compact design and value makes them cost effective. the 34717 is a pol dual output power supply. its integrated solution of fers a cost effectiv e system and reliable operation. it utilizes a voltage mode synchronous buck switching converter topology with integrated low r ds(on) (50 m ) n-channel power mosfets for higher efficiency operation. it provides an out put voltage with an accuracy of less than 2.0%, and capable of supplying up to 5.0 a of continuous current from both channels. the second output tracking abilities makes it i deal for systems with multiple related supply rails. it has a programmable switching frequency that allows for flexibility and optimization over the operating conditions and can operate at up to 1.0 mhz to significantly reduce the external components size and cost. it also provides the ability to program the over current limit for both channels. it protects against output over-current, over- voltage, under-voltage, and ov er-temperature conditions. it also protects the system from short circuit events. it incorporates a power good output signal to alert the host when a fault occurs. it can be enabled and disabled by controlling the sd pin, which offers power sequencing capabilities. by integrating the control/su pervisory circuitry along with the power mosfet switches for the buck converter into a space-efficient package, the 34717 offers a complete, small- size, cost-effective, and simple solution to satisfy the needs of today?s systems. functional pin description bootstrap input (boot1, boot2) bootstrap capacitor input pin. connect a capacitor (as discussed in bootstrap capacitor on page 21 ) between this pin and the sw pin of the respective channel to enhance the gate of the high side power mosfet during switching. power input voltage (pvin1, pvin2) buck converter power input voltag e. this is the drain of the buck converter high side power mosfet. switching node (sw1, sw2) buck converter switching node. this pin is connected to the output inductor. power ground (pgnd1, pgnd2) buck converter and discharge mosfets power ground. it is the source of the buck conv erter low side power mosfet. compensation input (comp1, comp2) buck converter external compensation network connects to this pin. use a type iii compensation network. error amplifier inverting input (inv1, inv2) buck converter error amplifier inverting input. connect the v ddq voltage (channel 1) to inv1 pin through a resistor divider and connect the v tt voltage (channel 2) directly to inv2 pin. internal supply volt age output (vddi) this is the output of the internal bias voltage regulator. connect a 1.0 f, 6.0 v low esr ceramic filter capacitor between this pin and the gnd pin. filtering any spikes on this output is essential to the in ternal circuitry stable operation. signal ground (gnd) analog ground of the ic. internal analog signals are referenced to this pin voltage. input supply voltage (vin) ic power supply input voltage. input filtering is required for the device to operate properly. power good output signal ( pg ) this is an active low open drain output that is used to report the status of the device to a host. this output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. this output activates after a 10 ms delay and must be pulled up by an external resistor to a supply voltage like v in .
analog integrated circuit device data freescale semiconductor 13 34717 functional description functional pin description shutdown input ( sd ) if this pin is tied to the gnd pin, the device will be in shutdown mode. if left unconnected or tied to the vin pin, the device will be in normal mode. the pin has an internal pull- up of 1.5 m . reference voltage input (vrefin) the output of channel two will track the voltage applied at this pin. frequency adjustme nt input (freq) the buck converters switching frequency can be adjusted by connecting this pin to an external resistor divider between vddi and gnd pins. the default switching frequency (freq pin connected to ground, gnd) is set at 1.0 mhz. soft start adjustment input (ilim1, ilim2) soft start can be adjusted by applying a voltage between 1.25 v and vddi on each ilim pin.
analog integrated circuit device data 14 freescale semiconductor 34717 functional description functional internal block description functional internal block description figure 4. block illustration internal bias circuits this block contains all circui ts that provide the necessary supply voltages and bias currents for the internal circuitry. it consists of: ? internal voltage supply regulator: this regulator supplies the v ddi voltage that is used to drive the digital/ analog internal circuits. it is equipped with a power-on- reset (por) circuit that watc hes for the right regulation levels. external filtering is needed on the vddi pin. this block will turn off during the shutdown mode. ? internal bandgap reference voltage: this supplies the reference voltage to some of the internal circuitry. ? bias circuit: this block generates the bias currents necessary to run all of the blocks in the ic. system control and logic this block is the brain of the ic where the device processes data and reacts to it . based on the status of the sd pin, the system control reacts accordingly and orders the device into the right status. it al so takes inputs from all of the monitoring/protection circuits and initiates power up or power down commands. it communicates with the buck converter to manage the switching operation and protects it against any faults. oscillator this block generates the clock cycles necessary to run the ic digital blocks. it also generates the buck converters switching frequency. the switching frequency can be programmed by connecting a resistor divider to the freq pin, between vddi and gnd pins (see figure 1 ). protection functions this block contains the following circuits: ? over-current limit and short-circuit detection: this block monitors the output of the buck converters for over- current conditions and short-circuit events and alerts the system control fo r further command. ? thermal limit detection: this block monitors the temperature of the device for overheating events. if the temperature rises abov e the thermal shutdown threshold, this block will alert the system control for further commands. ? output over-voltage and under-voltage monitoring: this block monitors the buck converters output voltages to ensure they are within regulati on boundaries. if not, this block alerts the system co ntrol for furt her commands. control and supervisory functions this block is used to interface with an outside host. it contains the following circuits. ? shutdown control input: an outside host can put the 34717 device into shutdown mode by sending a logic ?0? to the sd pin. ? power good output signal: the 34717 can communicate to an outside host that a fault has occurred by pulling the voltage on the pg pin high. mc34717 - functional block diagram internal bias circuits system control and logic oscillator protection functions control and supervisory functions tracking and sequencing 2 x buck converter
analog integrated circuit device data freescale semiconductor 15 34717 functional description functional internal block description tracking and sequencing this block allows the second output of the 34717 to track the voltage applied at the vrefin pin in different tracking configurations. this will be discussed in further details later in this document. for power down during a shutdown mode, the 34717 uses internal discharge mosfets (m8 and m9 on figure 2 , page 2 ) to discharge the first and second output respectively. the discharge mosfets are only active during shutdown mode. using this block along with controlling the sd pin can offer the user power sequencing capabilities by controlling when to turn the 34717 outputs on or off. buck converter this block provides the main function of the 34717: dc to dc conversion from an un-regulated input voltage to a regulated output voltage used by the loads for reliable operation. the buck converter is a high performance, fixed frequency (externally adjustable), synchronous buck pwm voltage-mode control. it drives integrated 50m n-channel power mosfets saving board space and enhancing efficiency. the switching regulator output voltage is adjustable with an accuracy of less than 2% to meet today?s requirements. the second channe l?s output has the ability to track the voltage applied at the vrefin pin. the regulator's voltage control loop is co mpensated using a type iii compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. a typica l bootstrap circuit with an internal pmos switch is used to provide the voltage necessary to properly enhance the high side mosfet gate. the 34717 has the ability to supply up to 5.0 a of continuous current from each channel, making it suitable for many high current applications.
analog integrated circuit device data 16 freescale semiconductor 34717 functional device operation operational modes functional device operation operational modes figure 5. operation modes diagram modes of operation the 34717 has two primary modes of operation: normal mode in normal mode, all func tions and outputs are fully operational. to be in this mode, the v in needs to be within its operating range, shutdown input is high, and no faults are present. this mode consumes the most amount of power. shutdown mode in this mode, activated by pulling the sd pin low, the chip is in a shutdown state and the output is disabled and discharged. in this mode, t he 34717 consumes the least amount of power since almost al l of the internal blocks are disabled. start-up sequence when power is first applied, the 34717 checks the status of the sd pin. if the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. once the sd pin is set to high, the v ddi internal supply voltage and the bias currents will be established, so the internal v ddi por signal can be released. the rest of the internal blocks will be enabled and the buck converter switching frequency and soft start timing values are dete rmined by reading the freq, ilim1, and ilim2 pins. a soft st art cycle is then initiated to ramp up the output of the buck converter. the first channel uses an internal 0.7 v reference for its e rror amplifier while the second channel?s error amp lifier uses the voltage on the vrefin pin as its reference voltage until v refin is equal to 0.7 v, then the error amplifier de faults to the internal 0.7 v reference voltage. this method allows the second output to achieve multiple tracking configurations as will be explained later in this document. soft start is used to prev ent the output voltage from overshooting during startup. at initial startup, the output capacitor is at zero volts; v out = 0 v. therefore, the voltage across the inductor will be pv in during the capacitor charge phase which will create a very sharp di/dt ramp. allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load normal f sw is programmed i lm1 , i lm2 are programmed v out1 and v out2 t ss = 1 v out1 = on v out2 = on pg = 0 shutdown f sw is programmed v out1 = discharge v out2 = discharge pg = 1 sd = 0 v in < 3.0 v v out1 <=v out1 v out1 >=v ovr1 t j >=170 c i out1 >=i lim1 for>=10 ms i out1 >=i short1 i out2 >=i short2 t j >= 170 c i out2 >=i lim2 for>=10 ms v out2 >=v ovr2 v out2 <=v uvf2 sd =1 3.0 v<=v in <=6.0 v v out1 >= v uvr1 v out1 <= v ovf1 t j <=145 c t imeout expired t imeout expired t imeout expired t imeout expired t imeout expired t j <=145 c t imeout expired v out2 <=v ovf2 v out2 =>=v uvr2 v out2 under-voltage v out1 =on v out2 =on pg = 1 v out2 over-voltage v out1 =on v out2 =on pg = 1 channel 2 thermal shutdown v out1 =on v out2 =off pg = 1 channel 2 over-current v out1 =on v out2 =off pg = 1 timeout=1 v out2 short-circuit v out1 =on v out2 =off pg = 1 timeout=1 v out1 short-circuit v out1 =off v out2 =on pg = 1 timeout=1 channel 1 over-current v out1 =off v out2 =on pg = 1 timeout=1 channel 1 thermal shutdown v out1 =off v out2 =on pg = 1 v out1 over-voltage v out1 =on v out2 =on pg = 1 v out1 under-voltage v out1 =on v out2 =on pg = 1 power off v out1 =off v out2 =off pg = 1
analog integrated circuit device data freescale semiconductor 17 34717 functional device operation operational modes current that can result in an undesired voltage spike once the capacitor is fully charged. the soft start is active each time the ic goes out of standby or shutdown mode, power is recycled, or after a fault retry. after a successful start-up cycle where the device is enabled, no faults have occurred, and the output voltage has reached its regulation point, the 34717 pulls the power good output signal low after a 10 ms reset delay, to indicate to the host that the device is in normal operation. protection functions the 34717 monitors the application for several fault conditions to protect the load fr om overstress. the reaction of the ic to these faults ranges from turning off the outputs to just alerting the host that something is wrong. in the following paragraphs, each fault c ondition is explained: output over-voltage an over-voltage condition occurs once the output voltage goes higher than the rising over-voltage threshold (v ovr ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, but the output will stay active. to avoid erroneous over-voltage conditions, a 20 s filter is implemented. the buck converter will use its feedback loop to attempt to correct the fault. once the output voltage falls below the falling over-voltage threshold (v ovf ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output under-voltage an under-voltage condition o ccurs once the output voltage falls below the falling under-voltage threshold (v uvf ). in this case, the power good output signal is pulled high, alerting the host that a fault is present, bu t the output will st ay active. to avoid erroneous under-voltage conditions, a 20 s filter is implemented. the buck converter will use its feedback loop to attempt to correct the fault. once the output voltage rises above the rising under-voltage threshold (v uvr ), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. output over-current this block detects over-curre nt in the power mosfets of the buck converter. it is co mprised of a sense mosfet and a comparator. the sense mosfet acts as a current detecting device by sampling a ratio of the load current. that sample is compared via the co mparator with an internal reference to determine if the out put is in over-current or not. if the peak current in the output inductor reaches the over current limit (i lim ), the converter will start a cycle-by-cycle operation to limit the current, and a 10 ms over-current limit timer (t lim ) starts. the converter will stay in this mode of operation until one of the following occurs: ? the current is reduced back to the normal level before t lim expires, and in this case normal operation is regained. ?t lim expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. at the end of a time-out period of 100 ms (t timeout ), the device will attempt another soft start cycle. ? the device reaches the thermal shutdown limit (t sdfet ) and turns off the output. the power good output signal is pulled high. ? the output current keeps increasing until it reaches the short-circuit current limit (i short ). see below for more details. short-circuit current limit this block uses the same cu rrent detection mechanism as the over-current limit detection block. if the load current reaches the i short value, the device reacts by shutting down the output immediately. this is necessary to prevent damage in case of a permanent short circuit. then, at the end of a timeout period of 100 ms (t timeout ), the device will attempt another soft start cycle. thermal shutdown thermal limit detection block monitors the te mperature of the device and protects agains t excessive heat ing. if the temperature reaches the thermal shutdown threshold (t sdfet ), the converter output switches off and the power good output signal indicates a fault by pulling high. the device will stay in this st ate until the temperature has decreased by the hysteresis value and then after a timeout period (t timeout ) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. if successful normal operation is regained, the power good output signal is asserted low to indicate it.
analog integrated circuit device data 18 freescale semiconductor 34717 typical applications typical applications boot1 pvin1 pvin1 sw1 sw1 pgnd1 pgnd1 vout1 inv1 comp1 vrefin nc pg sd comp2 inv2 vout2 pgnd2 pgnd2 sw2 sw2 pvin2 pvin2 boot2 ilim1 ilim2 freq vin gnd vddi nc vin boot1 sw1 c28 0.1 f 0.1 f c14 vddi pvin1 sw1 pgnd1 0.1 f c27 0.1 f c11 boot2 sw2 c15 0.1 f vout1 vout2 pvin2 sw2 pgnd2 vin freq ilim2 ilim1 vrefin 0.1 f c13 0.1 f c12 inv1 comp1 pg sd comp2 inv2 mc34717 1 2 3 4 5 6 7 8 9 10 11 13 12 14 15 16 17 18 19 20 21 22 23 24 25 26 2 3 4 15 16 17 c18 15 pf r15 22 k c19 0.75 nf r2 12.7 k c20 0.910 nf r14 560 r1 20 k comp1 vo1 c21 20 pf r19 15 k c22 1.8 nf r2 17.4 k c230 1.0 nf r18 300 r4 20 k comp2 vo2 inv2 inv2 compensation network sw1 compensation network sw2 buck converter 1 buck converter 2 vo1 c25 100 f c24 100 f c10 100 f r20 4.7_nopop c26 1n f_nopop d3 pmeg2010ea _nopop l1 1 h sw1 vo1_1 vo1_2 vo2 c8 100 f c7 100 f c6 100 f r30 4.7_nopop c9 1n f_nopop d2 omeg2010ea _nopop l1 1.5 h sw2 vo2_1 vo2_2
analog integrated circuit device data freescale semiconductor 19 34717 typical applications figure 6. 34717 typical application figure 7. 34717 typical application j2 j3 j4 pvin1 vo1 gnd 3 2 1 3 2 1 3 2 1 gnd gnd vo2 vin pvin2 vm vin c17 10 f c16 0.1 f r7 1k d1 led vin led vm vmaster r8 10k r9 10k stby_nopop vo1 vmaster led vrefin pg sd j1 sd con10a 1 1 1 2 2 2 3 4 56 7 8 9 10 r22 10 k_nopop r13 10 k_nopop r11 10 k_nopop r16 10 k r10 10 k r12 10 k vddi vddi vddi ilim1 ilim2 freq pvin1 c1 0.1 f c2 1 .0 f c3 100 f c4 100 f c5 100 f pvin2 c30 0.1 f c31 1 .0 f c32 1002 f c33 100 f c29 100 f vddi r21 pot_50 k_nopop r5 pot_50 k_nopop r6 pot_50 k_nopop ilim1 ilim2 freq i/o signals vin capacitors pgood led vmaster jumpers ilim1, ilim2, freq pvin1 capacitors pvin2 capacitors trimpots nopop x
analog integrated circuit device data 20 freescale semiconductor 34717 typical applications configuring the output voltage: both channels for the 34717 are general purpose dc-dc converters. the resistor divider to the inv node is responsible for setting the output voltage. the equation is: for channel 1: v ref =v bg =0.7v. for channel 2: the second channel of the 34717 has an internal reference selector, thus v ref can be either the voltage at vrefin terminal or the internal reference voltage v bg . the reference value is given by the following condition: v ref =vrefin if vrefin is less than v bg =0.7 v. otherwise, v ref =v bg . usually the output r egulation voltage is calculated using the internal reference v bg , and the condition v ref =vrefin is used for tracking purposes. switching frequency configuration the switching frequency will have a value of 1.0mhz by connecting the freq terminal to the gnd. if the smallest frequency value of 200 khz is desired, then connect the freq terminal to vddi. to pr ogram the switching frequency to another value, an external resistor divider must be connected to the freq terminal to achieve the voltages given by table 5 . table 5. frequency selection table soft start adjustment table 6 shows the voltage that should be applied to the ilim1and ilim2 pins to get the desired soft start timing. table 6. soft start configurations figure 8. resistor divider for frequency and soft start adjustment frequency voltage applied to pin freq 200 2.341 ? 2.500 253 2.185 - 2.340 307 2.029 - 2.184 360 1.873 - 2.028 413 1.717 ? 1.872 466 1.561 ? 1.716 520 1.405 - 1.560 573 1.249 - 1.404 627 1.093 - 1.248 ? ? ? ? ? ? + = 1 2 1 r r v v ref out 680 0.936 - 1.092 733 0.781 - 0.936 787 0.625 - 0.780 840 0.469 - 0.624 893 0.313 - 0.468 947 0.157 - 0.312 1000 0.000 - 0.156 soft start [ms] voltage applied to ilim 3.2 1.19 - 1.49 v 1.6 1.50 - 1.81 v 0.8 1.82 - 2.13 v 0.4 2.14 - 2.50 v r fqh r fql vddi freq gnd c vddi r ih r il ilim1 r ih r il
analog integrated circuit device data freescale semiconductor 21 34717 typical applications selecting inductor the inductor calculation process is the same for both channels. the equation is the following: selecting the output filter capacitor the following considerations are most important for the output capacitor, and not the act ual farad value: the physical size, the esr of the capacitor, and the voltage rating. calculate the minimum output capacitor using the following formula: transient response percentage: tr_% (use a recommended value of 2 to 4% to assure a good transient response.) maximum transient voltage: tr_v_dip = v out *tr_% maximum current step: inductor current rise time: the following formula is helpful to find the maximum allowed esr. the effects of the esr is often neglected by the design - ers and may present a hidden danger to the ultimate supply stability. poor quality capacitors have a widely disparate esr value, which can make the closed loop response incon - sistent. bootstrap capacitor the bootstrap capacitor is needed to supply the gate voltage for the high side mosfet. this n-channel mosfet needs a voltage difference between its gate and source to be able to turn on. the high side mosfet source is the sw node, so it is not at ground an d it is floating and shifting in voltage. we cannot just apply a vo ltage directly to the gate of the high side that is referenc ed to ground. we need a voltage referenced to the sw node. this is why the bootstrap capacitor is needed. this capacitor charges during the high side off time. the low side will be on during that time. the sw node and the bottom of the bootstrap capacitor will be connected to ground, and the top of the capacitor will be connected to a voltage source . the capacitor will charge up to that voltage sour ce (for example 5.0 v). now when the low side mosfet switches off and the high side mosfet switches on, the sw nodes will rise to v in , and the voltage on the boot pin will be v cap + v in . the gate of the high side will have v cap across it and it will be able to stay enhanced. a 0.1 f capacitor is a good value for this bootstrap element. type iii compensation network power supplies are desired to offer accurate and tight regulation output voltages. a high dc gain is required to accomplish this, but with high gain comes the possibility of instability. the pu rpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the cont rol-to-output transfer function that could jeopardized the stabil ity of the power supply. the type iii compensation network used for the 34717 comprises two poles (one integrator and one high frequency to cancel the zero generated from the esr of the output capacitor) and two zeros to cancel the two poles generated from the lc filter as shown in figure 9 . maximum off time percentage t switching period drain ? to ? source resistance of fet winding resistance of inductor output current ripple ls on rds _ ) ( w r _ out out out max i w r ls on rds i v t d l + + ? ? = )) _ _ ) ( ( * ( ' max _ 1 ' vin v d out max ? = out i dip v tr rise i dt i co out _ _ _ _ * = l fsw d vout vin step iout * max _ * ) min _ ( _ ? = step i i t rise i dt out out _ * _ _ = min) 1 ( * * max d v l fsw v esr out out ? =
analog integrated circuit device data 22 freescale semiconductor 34717 typical applications figure 9. type iii compensation network 1. choose a value for r1 2. consider a crossover frequency of one tenth of the switching frequency, set the zero pole frequency to fcross/10 3. knowing the lc frequency, the frequency of zero 1 and zero 2 in the compensation network are equal to f lc this gives the result 4. calculate r s by placing the first pole at the esr zero frequency 5. equating pole 2 to 5 times the crossover frequency achieves a faster response and a proper phase margin tracking configurations. this device allows two tracking configurations: ratiometric and co-incidental tracking. figure 10. ratiometric tracking figure 11. co-incidental tracking ratiometric tracking circuit configuration the master voltage feedback resistor divider network is used in place of r 3 and r 4 as shown in figure 12 . the slave output is connected through its own feedback resistor divider network to the inv- terminal, resistors r 1 and r 2 . all four sw x vout x inv x comp x l x r sx c sx c xx r fx c fx r1 x r2 x c ox f cross p c r f f 1 0 * 2 1 10 1 = = po f f r c 1 * 2 1 = f f z c r f * 2 1 1 = s z c r f 1 2 * 2 1 = 2 1 2 1 z z x x lc f f co l f = = = 1 * 2 1 z f f f c r = 2 1 * 2 1 z s f r c = s s p c r f * 2 1 1 = s p s c f r 1 * 2 1 = 1 * * 2 1 p x esr f esr co f = = 1 * 2 2 ? = p f f f x f c r c c 5 f ? cross f p2 1 2 r f c f c x c f c x + ------------------- - ? --------------------------------------- - == vmaster different slope vslave vmaster vslave slave regulation point same slope
analog integrated circuit device data freescale semiconductor 23 34717 typical applications resistors will affect the accura cy of the system and must be 1% accurate resistors. to achieve this tracking config uration, the master voltage must be connected in the way shown and cannot be directly connected to the vrefin terminal. figure 12. ratiometric tracking circuit connections equations ?v m = v bg_m (1+r 3 /r 4 ) ?v refin = v m * r 4 /(r 3 +r 4 ) ?v refout = v refin ?v s = v refout (1+r 1 /r 2 ) = v m * r 4 /(r 3 +r 4 )*(r 2 +r 1 )/r 2 , if v refout < v bg_s ?v s = v bg_s (1+r 1 /r 2 ), if v refout v bg_s figure 13. ratiometric tracking plot co-incidental tracking circuit configuration: connect a three resistor divider to the master voltage (v m ) and route the upper tap point of the divider to the vrefin terminal, resistors r 3 , r 4 , and r 5 as shown in figure 14 . this resistor divider must be the same ratio as the slave output?s (v s ) feedback resistor divider, which in turn connects to the inv- terminal, resistors r 1 and r 2 below ( condition: r 1 = r 3 and r 2 = r 4 + r 5 ) . the master?s feedback resistor divider would be (r 3 +r 4 ) and r 5 . all five resistors will affect the accuracy of the system and must be 1% accurate resistors. to achieve this tracking configuration, the master voltage must be connected in the way shown and cannot be directly connected to the vrefin terminal. figure 14. co-incidental tracking circuit connections equations ?v m = v bg_m [1+(r 3 +r 4 )/r 5 ] ?v refin = v m *(r 4 +r 5 )/(r 3 +r 4 +r 5 ) ?v refout = v refin ?v s = v refout (1+r 1 /r 2 ) = v m *(r 4 +r 5 )/ (r 3 +r 4 +r 5 )*(r 2 +r 1 )/r 2 = v m if v refout < v bg_s ?v s = v bg_s (1+r 1 /r 2 ), if v refout v bg_s figure 15. co-incidental tracking plot not-ddr mode (source only mode) is the case when no tracking is needed. vrefin should be connected to vddi and the reference selection block will use the internal band gap voltage as the error amplifier?s reference voltage. a user can potentially apply a voltage to the vrefin terminal directly or through a resistor divider to get a buffered output for use in the application. the condition here is, the voltage applied to the vrefin terminal is greater than v bg to guarantee that the reference selection block will not switch back to the v refout voltage. v slave inv comp rs r 1 cs r f c f c x ea vrefin reference selector v bg r3 r4 r 2 v master to inv- of vmaster + - c o v slave inv comp rs r 1 cs r f c f c x ea vrefin reference selector v bg r3 r4 r 2 v master to inv- of vmaster + - r5 c o
analog integrated circuit device data 24 freescale semiconductor 34717 typical applications layout guidelines the layout of any switching regulator requires careful consideration. first, there ar e high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage sp ikes they can create. to do this, an understanding of the major current carrying loops is important. see figure 16 . these loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. also, the current carry ing power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. if sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction . second, small signal components which connect to sensitive nodes need considerati on. the critical small signal components are the ones associated with the feedback circuit. the high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. other critical small signal components include the bypass capacitors for vin, vr efin, and vddi. locate the bypass capacitors as close to the pin as possible. the use of a multi-layer printed circuit board is recommended. dedicate one layer, usually the layer under the top layer, as a ground plane. make all critical component ground connections with vias to th is layer. make sure that the power grounds, pgnd1 and pgnd2 are connected directly to the ground plane and not routed through the thermal pad or analog ground. dedicate another layer as a power plane and split this plane into local areas for common voltage nets. the ic input supply (vin) should be connected with a dedicated trace to the input s upply. this will help prevent noise on the buck regulator's power inputs (pvin1 and pvin2) from injecting switching noise into the ic?s analog circuitry. in order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. it is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm. figure 16. current loop vin1 buck con vert er 1 h s sd loop current sd on loop curr ent hs on vin2 and 3 buck converter 2 and 3 hs ls loop current ls on loop curr ent hs on sw1 sw2 and 3 gnd2 and 3 buck converter 1 and 2 pgnd1 and 2 sw1 and 2 pvin1 and 2
analog integrated circuit device data freescale semiconductor 25 34717 packaging packaging dimensions packaging packaging dimensions ep suffix (pb_free) 26-pin qfn 98asa10728d issue 0
analog integrated circuit device data 26 freescale semiconductor 34717 packaging packaging dimensions ep suffix (pb-free) 26-pin qfn 98asa10728d issue 0
analog integrated circuit device data freescale semiconductor 27 34717 revision history revision history revision date description of changes 1.0 2/2006 ? pre-release version ? implemented revision history page 2.0 1/2007 ? initial release ? converted format from market assessment to product preview ? major updates to the data, form, and style 3.0 5/2007 ? changed feature fom 2% to 1%, relabeled to include soft start ? change references for 45 m integrated n-channel power mosfets to 50 m ? removed machine model in maximum ratings ? added channel 1 high side mosfet drain voltage range ? changed output voltage accuracy (12) , (13) ? changed soft start adjusting reference voltage range and short-circuit current limit ? changed high side n-ch power mosfet (m4) rds(on) (12) and low side n-ch power mosfet (m5) rds(on) (12) ? changed m2 rds(on) and pvin1 pin leakage current ? added channel 2 high side mosfet drain voltage range ? changed soft start adjusting reference voltage range ? changed short-circuit current limit ? changed high side n-ch power mosfet (m6) rds(on) (14) and low side n-ch power mosfet (m7) rds(on) (14) ? changed m3 rds(on) and pvin2 pin leakage current ? changed sd pin internal pull-up resistor ? changed channel 1 soft start duration (normal mode) , over-current limit retry timeout period , and output under-voltage/over-voltage filter delay timer ? changed channel 2 soft start duration (normal mode) , over-current limit retry timeout period , and output under-voltage/over-voltage filter delay timer ? changed oscillator default switching frequency ? changed pg reset delay and thermal shutdown retry timeout period (21) ? changed definition for soft start adjustment input (ilim1, ilim2) ? changed drawings in 34717 typical application ? changed table for soft start adjustment ? removed pc34717ep/r2 from the ordering information and added mc34717ep/r2 ? changed data sheet status to advance information 4.0 12/2007 ? made changes to switching node (sw1, sw2) pins , boot1, boot2 pins (referenced to sw1, sw2 pins respectively) , output under-voltage threshold , output over-voltage threshold , both channels of high side n-ch power mosfet (m4) rds(on) (12) , both channels of low side n-ch power mosfet (m5) rds(on) (12) , charge device model ? added machine model (mm) , both channels of sw2 leakage current (standby and shutdown modes) , both channels of ( error amplifier dc gain (14) , error amplifier unit gain bandwidth (14) , error amplifier slew rate (14) , error amplifier input offset (14) ) ? fixed drawing for type iii compensation network ? added pin 27 to figure 3 and the 34717 pin definitions ? added the section layout guidelines
mc34717 rev 4.0 12/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007-8. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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